1. Field of the Invention
The present invention relates to an integrated semiconductor cascode circuit with an emitter layer, a first base region, a second base region, an intermediate region, and a collector region. The first base region is located between the emitter layer and the intermediate region, and the second base region is located between the intermediate region and the collector region. The invention also further relates to a method for producing an integrated semiconductor cascode circuit.
2. Description of the Background Art
From U.S. Pat. No. 5,399,899 semiconductor cascode circuits with mesa structures of multiple layers are known. The structure of each layer stack in the mesa structures represents a cascode comprised of two transistors. Base terminals of the upper transistor lie in a plane with the emitter terminal of a mesa structure. Example applications for such cascodes are not given in U.S. Pat. No. 5,399,899. According to the disclosure in U.S. Pat. No. 5,399,899, the height of the specified stack of layers from the bottom collector layer to the top layer, which contains base terminals of the upper transistor and the emitter terminal, is 2800 nm.
A structure with such dimensions is not typically suitable for high-frequency applications with frequencies up to approximately 200 GHz, since the cutoff frequency is determined by the length of time for the charge carriers to traverse such layer stacks between the emitter and collector terminal. Layer stack thicknesses on the order of, e.g., less than 100 nm appear to be significantly more suitable for the specified frequencies. In principle, a reduction in the layer thickness results in a higher cutoff frequency due to the shorter distance that must be traveled by the charge carriers. However, a disadvantage is that the desired high breakdown voltage also decreases with decreasing layer thickness.
When reducing the layer thicknesses of a semiconductor cascode circuit of the aforementioned type, it is necessary to ensure, in particular, that the base regions of the semiconductor cascode circuit, whose layer thickness may be only a few nm, are connected in a low-resistance fashion to external, generally metallic, contacts. Conceptually, the base layers can be divided into inner regions and outer regions. The inner region is defined by the lateral extension of the pn junctions toward the adjacent emitter and collector layers, and the outer region is used to connect to the aforementioned metallic contacts. It is the outer regions of the base layers that generally dominate the connection resistance, which is to say the total resistance between the metal and inner base.
In order to minimize the connection resistance, so-called “link” implantations of dopants are known, which increase the conductivity in the region of the outer base and in the semiconductor region between the external contact and the base region. Instead of implanting the dopants, it is also possible to introduce them by diffusion processes.
The diffusion or implantation of dopants generally results in doped regions which, in contrast to the rather planar base regions, also have a non-negligible smearing in their vertical extent, with the doped regions usually extending beyond the base layer plane. Such terminal dopants adversely affect the capacitances and breakdown voltages between the base regions. Small capacitances and high breakdown voltages are desired.